The spec explicitly defines how CXL transactions map to the new FLIT mode. If you are building "Pooled Memory" resources, the PCIe 6.0 PDF is required reading to understand the timers and retry mechanisms.
To manage the higher error rates inherent to PAM4, Revision 6.0 introduces Flit (Flow Control Unit) based encoding PCI Express 6.0 Specification pci express base specification revision 60 pdf
Replaces the traditional NRZ (Non-Return-to-Zero) signaling. Instead of two voltage levels (0 or 1), PAM4 uses four levels, allowing it to carry 2 bits of data in the same time interval. FLIT Mode (Flow Control Unit): The spec explicitly defines how CXL transactions map
You can download the official PCI Express Base Specification Revision 6.0 PDF from the PCI SIG website. PAM4 uses four levels