Application processor (master) sends a command to the PMIC (slave) to lower CPU voltage during idle — all over SPMI.
The MIPI SPMI specification defines a high-speed, low-power interface for power management in SoC designs. The interface is designed to be scalable, flexible, and efficient, allowing for the management of multiple power domains and voltage regulators. mipi spmi specification pdf
: Enables efficient data movement with burst reads/writes (up to 16 bytes for 8-bit addressing). Application processor (master) sends a command to the
The full is available exclusively to MIPI Alliance members . : Enables efficient data movement with burst reads/writes
is the only legal place to get the complete, final specification:
Using the MIPI specification ensures interoperability between chips from different vendors (e.g., a Qualcomm processor with a TI PMIC).
The specification utilizes a simple physical layer to minimize pin count and design complexity: Two-Wire Setup : Consists of a bidirectional serial data line ( ) and a unidirectional clock line ( Device Capacity